1. Field of the Invention
The present invention relates in general to a sense amplifier enable signal generator for a semiconductor memory device, and more particularly to a sense amplifier enable signal generator for a dynamic random access memory (referred to hereinafter as DRAM) in which a counter and a comparator are provided to generate a sense amplifier enable signal as a control signal for a sense amplifier in the DRAM to operate the sense amplifier at a proper time without being affected by a process parameter, an operating voltage, temperature, etc.
2. Description of the Prior Art
First, the operation of a general DRAM will be described briefly with reference to FIGS. 1a to 1e.
FIGS. 1a to 1e are timing diagrams of signals related to the operation of a sense amplifier in the DRAM. First, when a row address strobe bar signal RASB, which is a main signal operating the DRAM, is made active low, a row address buffer receives a row address. A row decoding operation is performed to decode the row address received by the row address buffer to select a corresponding one of word lines of a cell array block. Then, data from cells connected to the selected word line WL are transferred to bit lines BL and /BL. At this time, a signal which indicates an operating time point of the sense amplifier is enabled to operate a sense amplifier drive circuit of the cell array block selected by the row address. As the sense amplifier drive circuit is operated, sense amplifier bias voltages have supply and ground voltage levels Vcc and Vss, respectively, thereby driving the sense amplifier. If the sense amplifier begins to be operated, a voltage difference between the bit lines BL and /BL is changed from a very small value to a large value. Under this condition, a column decoder selected by a column address turns on a column transfer transistor to transfer the data on the bit lines BL and /BL to data bus lines DB and /DB, respectively.
Noticeably, at the time that a small voltage difference of about 0.2-0.3 V is generated between the bit lines BL and /BL due to the data from the cells connected to the selected word line WL, a sense amplifier enable signal SE is made active to operate the sense amplifier (see FIG. 1e). However, in the case where the voltage difference between the bit lines BL and /BL does not have a sufficient value, a faulty operation occurs when the sense amplifier enable signal SE is made active to operate the sense amplifier.
FIG. 2 is a circuit diagram illustrating the construction of a conventional delay circuit which implements a time delay required between the row address strobe bar signal RASB and sense amplifier enable signal SE shown respectively in FIGS. 1b and 1e. As shown in this drawing, a time delay from an enable point of the row address strobe bar signal RASB till an active point of the sense amplifier enable signal SE is established by the coupling of inverters and capacitors. This conventional delay circuit is disadvantageous in that a delay value may be varied due to a process variation, a dynamic temperature variation and a supply voltage noise, resulting in a device failure. In the case where a large amount of design margin is introduced to overcome the above problem, a device access time is damaged.